1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits that use metal-oxide-semiconductor (MOS) transistors, has been increasing. With the increase in the degree of integration, MOS transistors used in the integrated circuits have been miniaturized to the nanometer scale. With such miniaturization of MOS transistors, there may be a problem in that it becomes difficult to suppress a leak current and the area occupied by circuits is not easily decreased from the viewpoint of ensuring a required amount of current. In order to address this problem, a surrounding gate transistor (SGT) has been proposed in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and the gate surrounds a pillar-shaped semiconductor layer (refer to, for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
By using, as a gate electrode, a metal rather than polysilicon, the depletion can be suppressed and the resistance of the gate electrode can be decreased. However, it is necessary to use a production process in which, in steps after the formation of a metal gate, metal contamination due to the metal gate is constantly considered.
In a MOS transistor in the related art, in order to combine a metal gate process with a high-temperature process, a metal gate-last process in which a metal gate is formed after a high-temperature process has been employed in manufacturing of products (refer to, IEDM 2007, K. Mistry et. al, pp. 247-250). A gate is formed using polysilicon, and an interlayer insulating film is then deposited. Subsequently, the polysilicon gate is exposed by chemical-mechanical polishing, the polysilicon gate is etched, and a metal is then deposited. Therefore, also in an SGT, in order to combine a metal gate process with a high-temperature process, it is necessary to use a metal gate-last process in which a metal gate is formed after a high-temperature process. In an SGT, since an upper portion of a pillar-shaped silicon layer is located at a position higher than a gate, a suitable approach for using a metal gate-last process is necessary.
In the metal gate-last process, a polysilicon gate is formed, and a diffusion layer is then formed by ion implantation. In an SGT, since an upper portion of a pillar-shaped silicon layer is covered with a polysilicon gate, a suitable approach is necessary.
When a silicon pillar becomes thin, it becomes difficult for impurities to exist in the silicon pillar because the density of silicon is 5×1022 atoms/cm3.
In an SGT in the related art, it has been proposed that the threshold voltage be determined by changing the work function of a gate material while an impurity concentration of a channel be controlled to be as low as 1017 cm3 or less (refer to, for example, Japanese Unexamined Patent Application Publication No. 2004-356314).
In a planar MOS transistor, it is disclosed that a sidewall in a LDD region is formed of polycrystalline silicon having the same conductivity type as a low-concentration layer, and that a surface carrier of the LDD region is induced due to the difference in work function thereof. With this structure, the impedance of the LDD region can be decreased compared with an LDD-type MOS transistor having an oxide film sidewall (refer to, for example, Japanese Unexamined Patent Application Publication No. 11-297984). Japanese Unexamined Patent Application Publication No. 11-297984 describes that the polycrystalline silicon sidewall is electrically insulated from a gate electrode. In addition, a drawing shows that the polycrystalline silicon sidewall and source/drain are insulated by an interlayer insulating film.